If a scalar (not superscalar) processor has multiple nonredundant functional units (a single FPU and a single ALU for example) and it issues an instruction to the FPU at a certain clock tick, could it issue another instruction to the ALU at the next clock tick so that both the FPU and the ALU are executing at the same time (lets say that FPU instructions take longer to execute than ALU instructions)? Or would that make the processor superscalar?
Unfortunately, I have not yet found a definite answer. After a rather long discussion in the #hardware channel on Freenode, one person said that such a processor would have to be superscalar. I need to get the opinion of several people on this matter though, especially since he seemed a little unsure of the answer he gave.
I asked for help on a hardware forum, but there have been no replies as of yet. I may search for a more technical hardware forum tomorrow.
Reposted from http://invisiblegdev.blogspot.com/
